`timescale 1ns / 1ps

module test_xmj_D_FF;
	reg D;
	reg CLK;
	wire Q;
	wire QN;
	xmj_D_FF uut (
		.D(D), 
		.CLK(CLK), 
		.Q(Q), 
		.QN(QN)
	);
	
	integer i;
	initial begin
		CLK = 0;
		D = 0;
		for(i = 0; i < 100; i = i + 1) begin
			#1;
			if(i % 5 == 0) CLK = ~CLK;
			if(i == 12) D = 1;
			if(i == 14) D = 0;
			if(i == 24) D = 1;
			if(i == 35) D = 0;
		end
	end
	
endmodule

